1. Field of the Invention
The present invention relates to a semiconductor integrated circuit device and more particularly, to a semiconductor integrated circuit device including n- and p-channel Insulated-Gate Field-Effect Transistors (IGFETs) laid out on a so-called Silicon-On-Insulator (SOI) substrate, which raises the integration level of electronic elements.
2. Description of the Prior Art
A Complementary Metal-Oxide-Semiconductor (CMOS) Sea-Of-Gates (SOG) array is a typical one of well-known Application Specific Integrated Circuits (ASICs)
FIG. 1 shows a conventional layout of a CMOS SOG array, which includes a logic block of a two-input NAND circuit shown in FIG. 19. FIGS. 2 and 3 show cross-sections along the lines II--II and III--III in FIG. 1, respectively.
In FIG. 1, four basic cells 1203 are horizontally aligned so that adjoining two ones of the cells 1203 have overlapped or commonly-used boundaries. Any one of the four cells 1203 forms a mirror image of another adjacent thereto. Although this layout includes a lot of basic cells in addition to the four basic cells 1203, they are not shown here for the sake of simplification.
A first rectangular area 1201 and a second rectangular area 1202 are separately formed and electrically isolated by an isolation area 1200 located between these areas 1201 and 1202. The first area 1201 includes p-channel MOSFETs horizontally aligned along the longitudinal axis of the area 1201. The second area 1202 includes n-channel MOSFETs horizontally aligned along the longitudinal axis of the area 1202.
In each of the basic cells 1203, three p.sup.+ -type rectangular diffusion regions (i.e., source/drain regions for the p-channel MOSFETs) are formed to be aligned horizontally in the first area 1201. Three n.sup.+ -type rectangular diffusion regions (i.e., source/drain regions for the n-channel MOSFETs) are formed to be aligned horizontally in the second area 1202. Two linear polysilicon gate electrodes are formed to be aligned vertically to be overlapped with the first and second areas 1201 and 1202. An inner half of an n.sup.+ -type rectangular contact region is formed to be aligned to the p.sup.+ -type diffusion regions. A p.sup.+ -type inner half of a rectangular contact region is formed to be aligned to the n.sup.+ -type diffusion regions. These two contact regions are located to be overlapped with the common boundary of the adjacent basic cells 1203.
In FIGS. 1, 2, and 3, only a second one of the basic cells 1203, which is next to a first one located at the left-hand-side end, is used for constituting a two-input NAND circuit shown in FIG. 19.
In the second one of the basic cells 1203, the p.sup.+ -type source/drain regions 1206a and 1206b and the corresponding gate electrode 1208a constitute one of the p-channel MOSFETs formed in the first area 1201. The p.sup.+ -type source/drain regions 1206b and 1206c and the corresponding gate electrode 1208b constitute another of the p-channel MOSFETs formed in the first area 1201. These two p-channel MOSFETs are electrically connected to each other by commonly using the source/drain regions 1206b.
Similarly, the n.sup.+ -type source/drain regions 1207a and 1207b and the corresponding gate electrode 1208a constitute one of the n-channel MOSFETs formed in the second area 1202. The n.sup.+ -type source/drain regions 1207b and 1207c and the corresponding gate electrode 1208b constitute another of the n-channel MOSFETs formed in the second area 1202. These two n-channel MOSFETs are electrically connected to each other by commonly using the source/drain regions 1207b.
In a third one of the cells 1203, the p.sup.+ -type source/drain regions 1206d and 1206e and the corresponding gate electrode 1208c constitute one of the p-channel MOSFETs formed in the first area 1201. The p.sup.+ -type source/drain regions 1206e and 1206f and the corresponding gate electrode 1208d constitute another of the p-channel MOSFETs formed in the first area 1201. These two p-channel MOSFETs are electrically connected to each other by commonly using the source/drain regions 1206e.
Similarly, the n.sup.+ -type source/drain regions 1207d and 1207e and the corresponding gate electrode 1208c constitute one of the n-channel MOSFETs formed in the second area 1202. The n.sup.+ -type source/drain regions 1207e and 1207f and the corresponding gate electrode 1208d constitute another of the n-channel MOSFETs formed in the second area 1202. These two n-channel MOSFETs are electrically connected to each other by commonly using the source/drain regions 1207e.
In a fourth one of the cells 1203, the p.sup.+ -type source/drain regions 1206g and 1206h and the corresponding gate electrode 1208e constitute one of the p-channel MOSFETs formed in the first area 1201. The p.sup.+ -type source/drain regions 1206h and 1206i and the corresponding gate electrode 1208f constitute another of the p-channel MOSFETs formed in the first area 1201. These two p-channel MOSFETs are electrically connected to each other by commonly using the source/drain regions 1206h.
Similarly, the n.sup.+ -type source/drain regions 1207g and 1207h and the corresponding gate electrode 1208e constitute one of the n-channel MOSFETs formed in the second area 1202. The n.sup.+ -type source/drain regions 1207h and 1207i and the corresponding gate electrode 1208f constitute another of the n-channel MOSFETs formed in the second area 1202. These two n-channel MOSFETs are electrically connected to each other by commonly using the source/drain regions 1207h.
At the common boundary of the first and second ones of the basic cells 1203, the n.sup.+ -type contact region 1204a and the p.sup.+ -type contact region 1205a are formed in the first and second areas 1201 and 1202, respectively.
A linear power supply line 1211 for supplying a power supply voltage or potential V.sub.DD is formed over the first region 1201 to extend horizontally along the longitudinal axis of the first area 1201. The power supply line 1211 is electrically connected to the p.sup.+ -type source/drain regions 1206a and 1206c and the n.sup.+ -type contact regions 1204a and 1204b through corresponding contact holes 1210.
A linear ground line 1212 for supplying a ground voltage or potential is formed over the second area 1202 to extend horizontally along the longitudinal axis of the second area 1202, where the ground line 1212 is parallel to the power supply line 1211. The ground line 1212 is electrically connected to the n.sup.+ -type diffusion region 1207c and the p.sup.+ -type contact regions 1205a and 1205b through corresponding contact holes 1210.
A metal wiring line 1213 is connected to the polysilicon gate electrode 1208a through the corresponding contact hole 1210. The wiring line 1213 is electrically connected to a first input terminal (not shown) of the two-input NAND circuit in FIG. 19, to which a first input signal A01 is applied.
A metal wiring line 1214 is connected to the polysilicon gate electrode 1208b through the corresponding contact hole 1210. The wiring line 1214 is electrically connected to a second input terminal (not shown) of the two-input NAND circuit in FIG. 19, to which a second input signal A02 is applied.
A metal wiring line 1215 is connected to the p.sup.+ -type source/drain region 1206b and the n.sup.+ -type source/drain region 1207a through the corresponding contact holes 1210, respectively. The wiring line 1215 is electrically connected to an output terminal (not shown) of the two-input NAND circuit in FIG. 19, from which an output signal X is derived.
As shown in FIGS. 2 and 3, an n-type well 1302 and a p-type well 1303 are formed in the surface area of a p-type single-crystal silicon substrate 303. The first area 1201, in which the p-channel MOSFETs are formed, is located in the n-type well 1302. The second area 1202, in which the n-channel MOSFETs are formed, is located in the p-type well 1303.
The power supply voltage or potential V.sub.DD is applied to the n-type well 1302 through the n.sup.+ -type contact regions 1204a and 1204b. The ground voltage or potential is applied to the p-type well 1303 through the p.sup.+ -type contact regions 1205a and 1205b.
Each of the basic cells 1203 is electrically isolated by an isolation oxide 1601 formed on the surface of the substrate 303. Each of the contact regions 1204a, 1204b, 1205a, and 1205b is isolated by the isolation oxide 1601.
As clearly shown in FIGS. 2 and 3, to decrease the electric resistance, the surface areas 1301 of each gate electrode, each source/drain region, and each contact region are made of silicide. In other words, the surfaces of each gate electrode, each source/drain region, and each contact region are covered with silicide layers 1301, respectively.
The reference numeral 1602 denotes a dielectric of each of the n- and p-channel MOSFETs. A lower part of the dielectric 1602 serves as a gate insulator and a pair of side parts thereof serve as sidewall spacers.
The reference numeral 1603 denotes an interlayer dielectric layer formed to cover the silicide layers 1301 and the uncovered dielectrics 1602 and the isolation oxide 1601. The power supply and ground lines 1211 and 1212 and the metal wiring lines 1213, 1214, and 1215 are located on the interlayer dielectric layer 1603.
With the above-described layout of the CMOS SOG array in FIGS. 1, 2, and 3 using a bulk semiconductor substrate, the isolation area 1200 needs to be formed between the first and second areas 1201 and 1202 (i.e., the n- and p-type wells 1302 and 1303) for the purpose of electrical isolation of the p- and n-type wells 1303 and 1302.
Also, since the power supply potential V.sub.DD is supplied to the p.sup.+ -type source/drain regions 1206a and 1206c through the corresponding contact holes 1210, the two p-channel MOSFETs using these regions 1206a and 1206c are parallel connected. The p.sup.+ -type diffusion regions 1206a and 1206c serve as source regions of the respective p-channel MOSFETs. The p.sup.+ -type diffusion regions 1206b serves as a common drain region for the p-channel MOSFETs.
Similarly, since the ground potential is supplied to the n.sup.+ -type source/drain region 1207c through the corresponding contact hole 1210, the n-channel MOSFET using the regions 1207c and 1207b is serially connected to the n-channel MOSFET using the n.sup.+ -type source/drain regions 1207a and 1207b. The n.sup.+ -type diffusion region 1207c serves as a source region of the corresponding n-channel MOSFET, the n.sup.+ -type diffusion region 1207a serves as a drain region of the corresponding n-channel. MOSFET, and the n.sup.+ -type diffusion region 1207b serves as source and drain regions of these two n-channel MOSFETs.
The p.sup.+ -type diffusion region 1206b is electrically connected to the n.sup.+ -type diffusion region 1207a by the metal wiring line 1215. The wiring lines 1213 and 1214 are electrically connected to the first and second input terminals of the two-input NAND circuit in FIG. 19, respectively.
Thus, the two-input NAND circuit is formed by using one of the basic cells 1203 in the conventional layout shown in FIGS. 1, 2, and 3. This is popular in an SOG array.
A two-input NOR circuit is often formed by using one of the basic cells 1203 instead of a two-input NAND circuit.
Like the conventional layout shown in FIGS. 1, 2, and 3, a typical basic cell of an SOG array has a layout of MOSFETs capable of implementation of a two-input NAND or two-input NOR circuit.
Also, in almost all of CMOS SOG arrays using a bulk semiconductor and standard cells, power supply and ground lines are arranged in parallel, and p- and n-channel MOSFETs are arranged along the power supply and ground lines. The p-channel MOSFETs are aligned in a row extending in parallel to the power supply and ground lines, and the n-channel MOSFETs are aligned in another row extending in parallel thereto. It is rare that the p- and n-channel MOSFETs are aligned in the same row. This is caused by the following reason.
To implement the p- and n-channel MOSFETs in the same row using the bulk CMOS technology, isolation regions are necessarily formed between adjoining MOSFETs. This degrades the integration level of the MOSFETs and other electronic elements in almost all CMOS circuits.
FIG. 4 shows another conventional layout of a CMOS SOG array, which includes a logic block of a 2-1 selector circuit shown in FIG. 6. This layout and its cross sections are the same as those in FIGS. 1, 2, and 3 except for the pattern of metal wiring lines and position of the contact holes. Therefore, the explanation about the same layout and configuration is omitted here for simplification of description by attaching the same reference symbols to the same or corresponding parts or members in FIG. 4.
In FIG. 4, the power supply line 1211 is electrically connected to the n.sup.+ -type contact regions 1204a and 1204b and the p.sup.+ -type source/drain regions 1206b and 1206h located in the first area 1201 through the corresponding contact holes 1210, respectively. The ground line 1212 is electrically connected to the p.sup.+ -type contact regions 1205a and 1205b and the n.sup.+ -type source/drain regions 1207b and 1207h located in the second area 1202 through the corresponding contact holes 1210, respectively.
A metal wiring line 1402 is formed to be connected to the polysilicon gate electrode 1208f through the corresponding contact hole 1210. The wiring line 1402 is electrically connected to a first input terminal (not shown) of the 2-1 selector circuit shown in FIG. 6, to which a first input signal A0 is applied.
A metal wiring line 1403 is formed to be connected to the polysilicon gate electrode 1208e through the corresponding contact hole 1210. The wiring line 1403 is electrically connected to a second input terminal (not shown) of the 2-1 selector circuit shown in FIG. 6, to which a second input signal B0 is applied.
A metal wiring line 1404 is formed to be connected to the polysilicon gate electrode 1208a through the corresponding contact hole 1210. The wiring line 1404 is electrically connected to a third input terminal (not shown) of the 2-1 selector circuit shown in FIG. 6, to which a select signal S is applied. The wiring line 1404 is further connected the polysilicon gate electrode 1208d.
A metal wiring line 1405 is formed to interconnect the p.sup.+ - and n.sup.+ -type type source/drain regions 1206c and 1207c through the corresponding contact holes 1210. The wiring line 1405 is electrically connected to an output terminal (not shown) of the 2-1 selector circuit shown in FIG. 6, from which an output signal X is derived.
A metal wiring line 1420 is formed to interconnect the p.sup.+ -type source/drain region 1206i and the n.sup.+ -type source/drain regions 1207i and 1207d through the corresponding contact holes 1210.
A metal wiring line 1421 is formed to interconnect the p.sup.+ -type source/drain regions 1206d and 1206g and the n.sup.+ -type source/drain regions 1207g and 1207f through the corresponding contact holes 1210.
A metal wiring line 1422 is formed to interconnect the p.sup.+ -type source/drain region 1206e, the n.sup.+ -type source/drain region 1207e, and the gate electrode 1208b through the corresponding contact holes 1210.
A metal wiring line 1423 is formed to interconnect the p.sup.+ -type source/drain region 1206f and the n.sup.+ -type source/drain region 1207d through the corresponding contact holes 1210.
A metal wiring line 1425 is formed to interconnect the p.sup.+ -type source/drain region 1206a and the n.sup.+ -type source/drain region 1207a through the corresponding contact holes 1210.
A metal wiring line 1424 is formed to interconnect the gate electrode 1208c and the wiring line 1425 through corresponding contact holes 1401. Thus, the gate electrode 1208c is electrically connected to the p.sup.+ -type source/drain region 1206a and the n.sup.+ -type source/drain region 1207a through the wiring lines 1424 and 1425.
Only the wiring line 1424 is located in a second wiring level, while the remaining wiring lines 1420, 1421, 1422, 1423, and 1425 and the power supply and ground lines 1211 and 1212 are located in a first wiring level. The first wiring level is located on the interlayer dielectric layer 1603 shown in FIGS. 2 and 3. The second wiring level is located over the first wiring level through another interlayer dielectric layer (not shown) formed on the interlayer dielectric layer 1603.
The p-channel MOSFET formed by the p.sup.+ -type source/drain regions 1206h and 1206i and the gate electrode 1208f and the n-channel MOSFET formed by the n.sup.+ -type source/drain regions 1207h and 1207i and the same gate electrode 1208f constitute an inverter 205a of the 2-1 selector circuit of FIG. 6.
The p-channel MOSFET formed by the p.sup.+ -type source/drain regions 1206g and 1206h and the gate electrode 1208e and the n-channel MOSFET formed by the n.sup.+ -type source/drain regions 1207g and 1207h and the same gate electrode 1208e constitute an inverter 205b of the 2-1 selector circuit of FIG. 6.
The p-channel MOSFET formed by the p.sup.+ -type source/drain regions 1206a and 1206b and the gate electrode 1208a and the n-channel MOSFET formed by the n.sup.+ -type source/drain regions 1207a and 1207b and the same gate electrode 1208a constitute an inverter 205c of the 2-1 selector circuit of FIG. 6.
The p-channel MOSFET formed by the p.sup.+ -type source/drain regions 1206b and 1206c and the gate electrode 1208b and the n-channel MOSFET formed by the n.sup.+ -type source/drain regions 1207b and 1207c and the same gate electrode 1208b constitute an inverter 205d of the 2-1 selector circuit of FIG. 6.
The inverted input signal A0 is transmitted to the n.sup.+ -type source/drain region 1207d through the wiring line 1420. The inverted input signal A0 is further transmitted to the p.sup.+ -type source/drain region 1206f through the wiring line 1423. The inverted input signal B0 is transmitted to the n.sup.+ -type source/drain region 1207f and the p.sup.+ -type source/drain region 1206d through the wiring line 1421. The p.sup.+ -type source/drain region 1206e and the n.sup.+ -type source/drain region 1207e are electrically connected to one another through the wiring line 1422.
Thus, the p- and n-channel MOSFETs using the gate electrode 1208c constitute the CMOS transfer gate 206a of the 2-1 selector circuit of FIG. 6. The p- and n-channel MOSFETs using the gate electrode 1208d constitute another CMOS transfer gate 206b thereof.
The select signal S is applied to the gate electrode 1208d through the wiring line 1404. The inverted select signal S is applied to the gate electrode 1208c through the wiring lines 1424 and 1425.
The wiring line 1422, through which the output signals of the first and second transfer gates 206a and 206b, is electrically connected to the gate electrode 1208d serving as the input terminal of the inverter 205d. The inverted input signal for the inverter 205d is derived from its output terminal as the output signal X.
In recent years, to increase the operation speed and to decrease the power consumption and the chip area due to the number diminishment of electronic elements, pass-transistor logic circuits have been used practically in CMOS logic Large-Scale Integrated circuits (LSIs).
The basic constituents of the pass transistors logic circuits are CMOS transfer gate circuit and a 2-1 selector circuit. The 2-1 selector circuit is formed by two CMOS transfer gate circuits. The 2-1 selector circuit is often used in a latch or flip-flop circuit also.
However, when the 2-1 selector circuit is constituted by using the bulk CMOS technology, metal wiring lines will occupy a comparatively large area of a cell block, as shown in FIG. 4. This results in degradation of the integration level of the macro cells and the LSI chip.
FIG. 4 shows the layout of the basic cells of an SOG array using the bulk CMOS technology. Even if the same SOG array is constituted by the popular standard cells, the 2-1 selector circuit shown in FIG. 6 will occupy approximately the same chip area as that of FIG. 4.
Additionally, the Japanese Non-Examined Patent Publication No. 6-140630, which was published in May 1994, discloses an improved semiconductor device having p- and n-channel thin-film transistors (TFTs). In this device, the source and drain electrodes of the p- and n-channel thin-film transistors constitute a p-n junction. The current and voltage characteristics of the p-n junction is improved by converting the neighborhood of the p-n junction to silicide.
As explained above, with the conventional MOSFET layout of a CMOS SOG array shown in FIG. 1, the p-channel MOSFETs are aligned in a row parallel to the power supply line 1211 and the n-channel MOSFETs are aligned in another row parallel to the ground line 1212. The row of the p-channel MOSFETs is located in the first area 1201 or n-type well 1302. The row of the n-channel MOSFETs is located in the second area 1202 or p-type well 1303. The isolation region 1200 is necessarily located between the n- and p-type wells 1202 and 1203.
Therefore, when the drain regions of the n- and p-channel MOSFETs are coupled together at a node such as an output node of a NAND gate, a metal wiring line needs to be used, which results in increase in occupation area of the wiring lines. This occupation area increase prevents the integration level of the macro cells and/or semiconductor chip from being increased.
This integration level degradation becomes conspicuous for the layout of CMOS transfer gate circuits and/or 2-1 selector circuits, which are basic components of the pass transistor, latch, and flip-flop circuits. The 2-1 selector circuit is formed by combining two CMOS transfer gate circuits.
Moreover, with the conventional semiconductor device disclosed in the Japanese Non-Examined Patent Publication No. 6-140630, the current and voltage characteristics of the p-n junction is improved. However, there is no disclosure nor teaching about the layout and interconnection of the p- and n-channel TFTs.